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cy7c1360c, cy7c1362c 9-mbit (256 k 36/512 k 18) pipelined sram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-05540 rev. *n revised september 25, 2012 9-mbit (256 k 36/512 k 18) pipelined sram features supports bus operation up to 200 mhz available speed grades: 200 mhz, and 166 mhz registered inputs and outputs for pipelined operation 3.3 v core power supply (v dd ) 2.5 v/3.3 v i/o operation (v ddq ) fast clock-to-output times ? 3.0 ns (for 200 mhz device) provide high performance 3-1-1-1 access rate user selectable burst counter supporting intel ? ? pentium ? interleaved or linear burst sequences separate processor and controller address strobes synchronous self-timed writes asynchronous output enable single cycle chip deselect available in pb-free 100-pin tqfp package, non pb-free 119-ball bga package, and 165-ball fbga package tqfp available with 3-chip enable and 2-chip enable ieee 1149.1 jtag-compatible boundary scan functional description the cy7c1360c/cy7c1362c sram integrates 256 k 36 and 512 k 18 sram cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. all synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (clk). the synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (ce 1 ), depth-expansion chip enables (ce 2 and ce 3 [1] ), burst control inputs (adsc , adsp , and adv ), write enables (bw x , and bwe ), and global write (gw ). asynchronous inputs include the output enable (oe ) and the zz pin. addresses and chip enables are registered at the rising edge of clock when either address strobe processor (adsp ) or address strobe controller (adsc ) are active. subsequent burst addresses can be internally generated as controlled by the advance pin (adv ). address, data inputs, and write controls are registered on-chip to initiate a self-timed write cycl e.this part supports byte write operations (see pin definitions on page 8 and truth table on page 11 for further details). write cycles can be one to two or four bytes wide as controlled by the byte write control inputs. gw when active low cause s all bytes to be written. the cy7c1360c/cy7c1362c operate from a +3.3 v core power supply while all outputs may operate with either a +2.5 or +3.3 v supply. all inputs and outputs are jedec-standard jesd8-5-compatible. selection guide description 200 mhz 166 mhz unit maximum access time 3.0 3.5 ns maximum operating current 220 180 ma maximum cmos standby current 40 40 ma note 1. ce 3 is for a version of tqfp (3 chip enable option) and 165-ball fbga package only. 119-ball bga is offered only in 2 chip enable.
cy7c1360c, cy7c1362c document number: 38-05540 rev. *n page 2 of 37 logic block diagram ? cy7c1360c address register adv clk burst counter and logic clr q1 q0 adsp adsc mode bwe gw ce 1 ce 2 ce 3 oe enable register output registers sense amps output buffers e pipelined enable input registers a 0, a1, a bw b bw c bw d bw a memory array dqs dqp a dqp b dqp c dqp d sleep control zz a [1:0] 2 dq a , dqp a byte write register dq b , dqp b byte write register dq c , dqp c byte write register dq d , dqp d byte write register dq a , dqp a byte write driver dq b , dqp b byte write driver dq c , dqp c byte write driver dq d ,dqp d byte write driver logic block diagra cyc1362c a 0, a1, a address register adv clk burst counter and logic clr q1 q0 adsc bw b bw a ce 1 dq b, dqp b write register dq a, dqp a write register enable register oe sense amps memory array adsp 2 mode ce2 ce3 gw bwe pipelined enable dqs dqp a dqp b output registers input registers e dq a, dqp a write driver output buffers dq b, dqp b write driver a[1:0] zz sleep control
cy7c1360c, cy7c1362c document number: 38-05540 rev. *n page 3 of 37 contents pin configurations ........................................................... 4 pin definitions .................................................................. 8 functional overview ........................................................ 9 single read accesses ................................................ 9 single write accesses initia ted by adsp ................... 9 single write accesses initiate d by adsc ................. 10 burst sequences ....................................................... 10 sleep mode ............................................................... 10 interleaved burst address tabl e ............................... 10 linear burst address table ....................................... 10 zz mode electrical characteri stics ............................ 10 truth table ...................................................................... 11 partial truth table for read/write ................................ 12 partial truth table for read/write ................................ 12 ieee 1149.1 serial boundary sc an (jtag) ... ........... .... 13 disabling the jtag feature ...................................... 13 test access port (tap) ............................................. 13 performing a tap r eset .......... .............. .......... 13 tap registers ...................................................... 13 tap instruction set ................................................... 13 tap controller state diagram ....................................... 15 tap controller block diagram ...................................... 16 tap timing ...................................................................... 16 tap ac switching characteristics ............................... 17 3.3 v tap ac test conditions ....................................... 17 3.3 v tap ac output load equivalent ......................... 17 2.5 v tap ac test conditions ....................................... 17 2.5 v tap ac output load equivalent ......................... 17 tap dc electrical characteristics and operating conditions ..................................................... 18 identification register definitions ................................ 19 scan register sizes ....................................................... 19 instruction codes ........................................................... 19 boundary scan order .................................................... 20 boundary scan order .................................................... 21 maximum ratings ........................................................... 22 operating range ............................................................. 22 neutron soft error immunity ......................................... 22 electrical characteristics ............................................... 22 capacitance .................................................................... 23 thermal resistance ........................................................ 23 ac test loads and waveforms ..................................... 24 switching characteristics .............................................. 25 switching waveforms .................................................... 26 ordering information ...................................................... 30 ordering code definitions ..... .................................... 30 package diagrams .......................................................... 31 acronyms ........................................................................ 34 document conventions ................................................. 34 units of measure ....................................................... 34 document history page ................................................. 35 sales, solutions, and legal information ...................... 37 worldwide sales and design s upport ......... .............. 37 products .................................................................... 37 psoc solutions ......................................................... 37
cy7c1360c, cy7c1362c document number: 38-05540 rev. *n page 4 of 37 pin configurations figure 1. 100-pin tqfp (14 20 1.4 mm) pinout (3 chip enables - a version) a a a a a 1 a 0 nc/72m nc/36m v ss v dd nc/18m a a a a a a a a dqp b dq b dq b v ddq v ssq dq b dq b dq b dq b v ssq v ddq dq b dq b v ss nc v dd zz dq a dq a v ddq v ssq dq a dq a dq a dq a v ssq v ddq dq a dq a dqp a dqp c dq c dqc v ddq v ssq dq c dq c dq c dq c v ssq v ddq dq c dq c v dd nc v ss dq d dq d v ddq v ssq dq d dq d dq d dq d v ssq v ddq dq d dq d dqp d a a ce 1 ce 2 bw d bw c bw b bw a ce 3 v dd v ss clk gw bwe oe adsc adsp adv a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 mode cy7c1360c (256 k 36) nc
cy7c1360c, cy7c1362c document number: 38-05540 rev. *n page 5 of 37 figure 2. 100-pin tqfp (14 20 1.4 mm) pinout (2 chip enables - aj version) pin configurations (continued) a a a a a 1 a 0 nc/72m nc/36m v ss v dd nc/18m nc a a a a a a a dqp b dq b dq b v ddq v ssq dq b dq b dq b dq b v ssq v ddq dq b dq b v ss nc v dd zz dq a dq a v ddq v ssq dq a dq a dq a dq a v ssq v ddq dq a dq a dqp a dqp c dq c dq c v ddq v ssq dq c dq c dq c dq c v ssq v ddq dq c dq c v dd nc v ss dq d dq d v ddq v ssq dq d dq d dq d dq d v ssq v ddq dq d dq d dqp d a a ce 1 ce 2 bw d bw c bw b bw a a v dd v ss clk gw bwe oe adsc adsp adv a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 mode cy7c1360c (256 k 36) nc a a a a a 1 a 0 nc/72m nc/36m v ss v dd a a a a a a a a nc nc v ddq v ssq nc dqp a dq a dq a v ssq v ddq dq a dq a v ss nc v dd zz dq a dq a v ddq v ssq dq a dq a nc nc v ssq v ddq nc nc nc nc nc nc v ddq v ssq nc nc dq b dq b v ssq v ddq dq b dq b v dd nc v ss dq b dq b v ddq v ssq dq b dq b dqp b nc v ssq v ddq nc nc nc a a ce 1 ce 2 nc nc bw b bw a a v dd v ss clk gw bwe oe adsc adsp adv a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 mode cy7c1362c (512 k 18) nc nc/18m nc
cy7c1360c, cy7c1362c document number: 38-05540 rev. *n page 6 of 37 figure 3. 119-ball bga (14 22 2.4 mm) pinout (2 chip enables with jtag) pin configurations (continued) 234567 1 a b c d e f g h j k l m n p r t u v ddq nc/288m nc/144m dqp c dq c dq d dq c dq d aa aa adsp v ddq ce 2 a dq c v ddq dq c v ddq v ddq v ddq dq d dq d nc nc v ddq v dd clk v dd v ss v ss v ss v ss v ss v ss v ss v ss nc/576m nc/1g nc nc tdo tck tdi tms nc/36m nc/72m nc v ddq v ddq v ddq aaa a a a a a a a a a0 a1 dq a dq c dq a dq a dq a dq b dq b dq b dq b dq b dq b dq b dq a dq a dq a dq a dq b v dd dq c dq c dq c v dd dq d dq d dq d dq d adsc nc ce 1 oe adv gw v ss v ss v ss v ss v ss v ss v ss v ss dqp a mode dqp d dqp b bw b bw c nc v dd nc bw a nc bwe bw d zz cy7c1360c (256 k 36)
cy7c1360c, cy7c1362c document number: 38-05540 rev. *n page 7 of 37 figure 4. 165-ball fbga (13 15 1.4 mm) pinout (3 chip enables with jtag) pin configurations (continued) cy7c1360c (256 k 36) 234 567 1 a b c d e f g h j k l m n p r tdo nc/288m nc/144m dqp c dq c dqp d nc dq d ce 1 bw b ce 3 bw c bwe a ce2 dq c dq d dq d mode nc dq c dq c dq d dq d dq d nc/36m nc/72m v ddq bw d bw a clk gw v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss nc/18m v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck v ss tdi a a dq c v ss dq c v ss dq c dq c v ss v ss v ss v ss v ss nc v ss a1 dq d dq d nc nc v ddq v ss tms 891011 a adv a adsc nc oe adsp a nc/576m v ss v ddq nc/1g dqp b v ddq v dd dq b dq b dq b nc dq b nc dq a dq a v dd v ddq v dd v ddq dq b v dd nc v dd dq a v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq dq a v ddq a a v ss a a a dq b dq b dq b zz dq a dq a dqp a dq a a v ddq a a0 a v ss
cy7c1360c, cy7c1362c document number: 38-05540 rev. *n page 8 of 37 pin definitions name i/o description a 0 , a 1 , a input- synchronous address inputs used to select one of the address locations . sampled at the rising edge of the clk if adsp or adsc is active low, and ce 1 , ce 2 , and ce 3 [2] are sampled active. a1:a0 are fed to the two-bit counter. bw a , bw b , bw c , bw d input- synchronous byte write select inputs, active low . qualified with bwe to conduct byte writes to the sram. sampled on the rising edge of clk. gw input- synchronous global write enable input, active low . when asserted low on the rising edge of clk, a global write is conducted (all bytes are writt en, regardless of the values on bw x and bwe ). bwe input- synchronous byte write enable input, active low . sampled on the rising edge of clk. this signal must be asserted low to conduct a byte write. clk input- clock clock input . used to capture all synchronous inputs to the device. also used to increment the burst counter when adv is asserted low, during a burst operation. ce 1 input- synchronous chip enable 1 input, active low . sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 [2] to select/deselec t the device. adsp is ignored if ce 1 is high. ce 1 is sampled only when a new external address is loaded. ce 2 input- synchronous chip enable 2 input, active high . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 [2] to select/deselect the device. ce 2 is sampled only when a new external address is loaded. ce 3 [2] input- synchronous chip enable 3 input, active low . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select/deselect the device. not available for aj package version. not connected for bga. where referenced, ce 3 [2] is assumed active throughout this document for bga. ce 3 is sampled only when a new external address is loaded. oe input- asynchronous output enable, asynchronous input, active low . controls the direction of the i/o pins. when low, the i/o pins behave as outputs. when deasserted high , i/o pins are tristated, and act as input data pins. oe is masked during the first clock of a read cycle when emerging fr om a deselected state. adv input- synchronous advance input signal, sampled on the rising edge of clk, active low . when asserted, it automatically increments t he address in a burst cycle. adsp input- synchronous address strobe from processor, sampled on the rising edge of clk, active low . when asserted low, addresses presented to the device are captured in the address registers. a1:a0 are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. asdp is ignored when ce 1 is deasserted high. adsc input- synchronous address strobe from controller, sampled on the rising edge of clk, active low . when asserted low, addresses presented to the device are captured in the address registers. a1:a0 are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. zz input- asynchronous zz ?sleep? input, active high . when asserted high places the device in a non-time-critical ?sleep? condition with data integrity preserved. for normal operat ion, this pin has to be low or left floating. zz pin has an internal pull-down. dqs, dqp x i/o- synchronous bidirectional data i/o lines . as inputs, they feed into an on-chip data register that is triggered by the rising edge of clk. as outputs, they deliver the dat a contained in the memory location specified by the addresses presented during the prev ious clock rise of the read cycle. the direction of the pins is controlled by oe . when oe is asserted low, the pins behave as outputs. when high, dqs and dqp x are placed in a tristate condition. v dd power supply power supply inputs to the core of the device . v ss ground ground for the core of the device . v ssq i/o ground ground for the i/o circuitry . v ddq i/o power supply power supply for the i/o circuitry . mode input- static selects burst order . when tied to gnd selects linear burst sequence. when tied to v dd or left floating selects interleaved burst sequence. this is a strap pi n and should remain static during device operation. mode pin has an internal pull-up. note 2. ce 3 is for a version of 100-pin tqfp (3 chip enable option) and 165-ball fbga package only. 119-ball bga is offered only in 2 chip enable.
cy7c1360c, cy7c1362c document number: 38-05540 rev. *n page 9 of 37 functional overview all synchronous inputs pass through input registers controlled by the rising edge of the clock. all data outputs pass through output registers controlled by the ri sing edge of the clock. maximum access delay from the clock rise (t co ) is 3.0 ns (200 mhz device). the cy7c1360c/cy7c1362c supports secondary cache in systems using either a linear or interleaved burst sequence. the interleaved burst order supports pentium and i486 ? processors. the linear burst sequence is suited for processors that use a linear burst sequence. the burst order is user selectable, and is determined by sampling the mode input. accesses can be initiated with either the processor address strobe (adsp ) or the controller addre ss strobe (adsc ). address advancement through the burst sequence is controlled by the adv input. a two-bit on-chip wraparound burs t counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. byte write operations are qualified with the byte write enable (bwe ) and byte write select (bw x ) inputs. a global write enable (gw ) overrides all byte write inputs and writes data to all four bytes. all writes are simplif ied with on-chip synchronous self-timed write circuitry. three synchronous chip selects (ce 1 , ce 2 , ce 3 [3] ) and an asynchronous output enable (oe ) provide for easy bank selection and output tristate control. adsp is ignored if ce 1 is high. single read accesses this access is initiated when the following conditions are satisfied at clo ck rise: (1) adsp or adsc is asserted low, (2) ce 1 , ce 2 , ce 3 [3] are all asserted active, and (3) the write signals (gw , bwe ) are all deasserted high. adsp is ignored if ce 1 is high. the address presented to the address inputs (a) is stored into the address advancement logic and the address register while being presented to the memory array. the corresponding data is allowed to propagate to the input of the output registers. at the rising edge of the next clock, the data is allowed to propagate through the output register and on the data bus within 3.0 ns (200 mhz device) if oe is active low. the only exception occurs when the sram is emerging from a deselected state to a selected state, its outputs are always tristated during the first cycle of the access. af ter the first cycle of the access, the outputs are controlled by the oe signal. consecutive single read cycles are supported. after t he sram is deselected at clock rise by the chip select and either adsp or adsc signals, its output tristates immediately. single write accesses initiated by adsp this access is initiated when both of the following conditions are satisfied at clock rise: (1) adsp is asserted low and (2) ce 1 , ce 2 , ce 3 [3] are all asserted active. the address presented to a is loaded into the address register and the address advancement logic while being delivered to the memory array. the write signals (gw , bwe , and bw x ) and adv inputs are ignored during this first cycle. adsp -triggered write accesses require two clock cycles to complete. if gw is asserted low on th e second clock rise, the data presented to the dqs inputs is written into the corresponding address location in the memory array. if gw is high, then the write operation is controlled by bwe and bw x signals. the cy7c1360c/cy7c1362c provides byte write capability that is described in the write cycle descriptions table. asserting the byte write enable input (bwe ) with the selected byte write (bw x ) input, will selectively write to only the desired bytes. bytes not selected during a byte write operation remain unaltered. a synchronous self-timed write mechanism has been provided to simplify the write operations. because the cy7c1360c/cy7c1362c is a common i/o device, the output enable (oe ) must be deasserted high before presenting data to the dqs inputs. doing so tristates the output drivers. as a safety precaution, dqs are automatically tristated whenever a write cycle is detected, regardless of the state of oe . tdo jtag serial output synchronous serial data-out to the jtag circuit . delivers data on the negative edge of tck. if the jtag feature is not being used, this pin should be disconnected. this pin is not available on tqfp packages. tdi jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising edge of tck. if the jtag feature is not being used, this pin can be disconnected or connected to v dd . this pin is not available on tqfp packages. tms jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising edge of tck. if the jtag feature is not being used, this pin can be disconnected or connected to v dd . this pin is not available on tqfp packages. tck jtag- clock clock input to the jtag circuitry . if the jtag feature is not being used, this pin must be connected to v ss . this pin is not available on tqfp packages. nc ? no connects . not internally connected to the die nc (18, 36, 72, 144, 288, 576, 1g) ? these pins are not connected . they will be used for expansion to the 18m, 36m, 72m, 144m 288m, 576m, and 1g densities. pin definitions (continued) name i/o description note 3. ce 3 is for a version of tqfp (3 chip enable option) and 165-ball fbga package only. 119-ball bga is offered only in 2 chip enable.
cy7c1360c, cy7c1362c document number: 38-05540 rev. *n page 10 of 37 single write accesses initiated by adsc adsc write accesses are initiated when the following conditions are satisfied: (1) adsc is asserted low, (2) adsp is deasserted high, (3) ce 1 , ce 2 , ce 3 [4] are all asserted active, and (4) the appropriate combination of the write inputs (gw , bwe , and bw x ) are asserted active to conduct a write to the desired byte(s). adsc -triggered write accesses require a single clock cycle to complete. the address presented to a is loaded into the address register and the address advancement logic while being delivered to the memory array. the adv input is ignored during this cycle. if a global write is conducted, the data presented to the dqs is written into the corresponding address location in the memory core. if a byte write is co nducted, only the selected bytes are written. bytes not selected during a byte write operation remains unaltered. a synchrono us self-timed write mechanism has been provided to simplify the write operations. because the cy7c1360c/cy7c1362c is a common i/o device, the output enable (oe ) must be deasserted high before presenting data to the dqs inputs. doing so tristates the output drivers. as a safety precaution, dqs are automatically tristated whenever a write cycle is detected, regardless of the state of oe . burst sequences the cy7c1360c/cy7c1362c provides a two-bit wraparound counter, fed by a1:a0, that implements either an interleaved or linear burst sequence. the in terleaved burst sequence is designed specifically to support intel pentium applications. the linear burst sequence is designed to support processors that follow a linear burst sequence. the burst sequence is user selectable through the mode input. asserting adv low at clock rise auto matically increments the burst counter to the next addre ss in the burst sequence. both read and write burst operations are supported. sleep mode the zz input pin is an asynchronous input. asserting zz places the sram in a power conservation ?sleep? mode. two clock cycles are required to en ter into or exit from this ?sleep? mode. while in this mode, data inte grity is guaranteed. accesses pending when entering the ?sleep? mode are not considered valid nor is the completion of the operation guaranteed. the device must be deselected prior to entering the ?sleep? mode. ce 1 , ce 2 , ce 3 [4] , adsp , and adsc must remain inacti ve for the duration of t zzrec after the zz input returns low. interleaved burst address table (mode = floating or v dd ) first address a1:a0 second address a1:a0 third address a1:a0 fourth address a1:a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd) first address a1:a0 second address a1:a0 third address a1:a0 fourth address a1:a0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 zz mode electrical characteristics parameter description test conditions min max unit i ddzz sleep mode standby current zz > v dd ? ? 0.2 v ? 50 ma t zzs device operation to zz zz > v dd ? 0.2 v ? 2t cyc ns t zzrec zz recovery time zz < 0.2 v 2t cyc ?ns t zzi zz active to sleep current th is parameter is sampled ? 2t cyc ns t rzzi zz inactive to exit sleep current this parameter is sampled 0 ? ns note 4. ce 3 is for a version of 100-pin tqfp (3 chip enable option) and 165-ball fbga package only. 119-ball bga is offered only in 2 chip enable.
cy7c1360c, cy7c1362c document number: 38-05540 rev. *n page 11 of 37 truth table the truth table for cy7c1360c and cy7c1362c follows. [5, 6, 7, 8, 9, 10] operation address used ce 1 ce 2 ce 3 zz adsp adsc adv write oe clk dq deselect cycle, power-down none h x x l x l x x x l?h tri-state deselect cycle, power-down none l l x l l x x x x l?h tri-state deselect cycle, power-down none l x h l l x x x x l?h tri-state deselect cycle, power-down none l l x l h l x x x l?h tri-state deselect cycle, power-down none l x h l h l x x x l?h tri-state sleep mode, power-down none x x x h x x x x x x tri-state read cycle, begin burst external l h l l l x x x l l?h q read cycle, begin burst external l h l l l x x x h l?h tri-state write cycle, begin burst external l h l l h l x l x l?h d read cycle, begin burst external l h l l h l x h l l?h q read cycle, begin burst external l h l l h l x h h l?h tri-state read cycle, continue burst next x x x l h h l h l l?h q read cycle, continue burst next x x x l h h l h h l?h tri-state read cycle, continue burst next h x x l x h l h l l?h q read cycle, continue burst next h x x l x h l h h l?h tri-state write cycle, continue burst next x x x l h h l l x l?h d write cycle, continue burst next h x x l x h l l x l?h d read cycle, suspend burst current x x x l h h h h l l?h q read cycle, suspend burst current x x x l h h h h h l?h tri-state read cycle, suspend burst current h x x l x h h h l l?h q read cycle, suspend burst current h x x l x h h h h l?h tri-state write cycle, suspend burst current x x x l h h h l x l?h d write cycle, suspend burst current h x x l x h h l x l?h d notes 5. x = ?don't care.? h = logic high, l = logic low. 6. write = l when any one or more byte write enable signals and bwe = l or gw = l. write = h when all byte write enable signals, bwe , gw = h. 7. the dq pins are controlled by the current cycle and the oe signal. oe is asynchronous and is not sampled with the clock. 8. ce 1 , ce 2 , and ce 3 are available only in the tqfp package. bga package has only two chip selects ce 1 and ce 2 . 9. the sram always initiates a read cycle when adsp is asserted, regardless of the state of gw , bwe , or bw x . writes may occur only on subsequent clocks after the adsp or with the assertion of adsc . as a result, oe must be driven high prior to the start of the write cycle to allow the outputs to tri-state. oe is a don't care for the remainder of the write cycle. 10. oe is asynchronous and is not sampled with t he clock rise. it is masked internally during write cycles. during a read cycle all d ata bits are tri-state when oe is inactive or when the device is deselected, and all data bits behave as output when oe is active (low).
cy7c1360c, cy7c1362c document number: 38-05540 rev. *n page 12 of 37 partial truth table for read/write the partial truth table for read/write for cy7c1360c follows. [11, 12] function (cy7c1360c) gw bwe bw d bw c bw b bw a read h h x x x x read hlhhhh write byte a ? (dq a and dqp a )hlhhhl write byte b ? (dq b and dqp b )hlhhlh write bytes b, a h l h h l l write byte c ? (dq c and dqp c )hlhlhh write bytes c, a h l h l h l write bytes c, b h l h l l h write bytes c, b, a h l h l l l write byte d ? (dq d and dqp d )hllhhh write bytes d, a h l l h h l write bytes d, b h l l h l h write bytes d, b, a h l l h l l write bytes d, c h l l l h h write bytes d, c, a h l l l h l write bytes d, c, b h l l l l h write all bytes hlllll write all bytes l x x x x x partial truth table for read/write the partial truth table for read/write for cy7c1362c follows. [11, 12] function (cy7c1362c) gw bwe bw b bw a read h h x x read h l h h write byte a ? (dq a and dqp a )hlhl write byte b ? (dq b and dqp b )hllh write bytes b, a h l l l write all bytes h l l l write all bytes l x x x notes 11. the dq pins are controlled by the current cycle and the oe signal. oe is asynchronous and is not sampled with the clock. 12. table only lists a partial listing of the byte write combinations. any combination of bw x is valid. appropriate write will be done based on which byte write is active.
cy7c1360c, cy7c1362c document number: 38-05540 rev. *n page 13 of 37 ieee 1149.1 serial boundary scan (jtag) the cy7c1360c incorporates a serial boundary scan test access port (tap) in the bga package only. the tqfp package does not offer this functionality. this part operates in accordance with ieee standard 1149.1-1900, but does not have the set of functions required for full 1149.1 compliance. these functions from the ieee specification are excluded because their inclusion places an added delay in the critical speed path of the sram. note that the tap controller func tions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant taps. the tap operates using jedec-standard 3.3 v or 2.5 v i/o logic levels. the cy7c1360c contains a tap controller, instruction register, boundary scan register, bypass register, and id register. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap co ntroller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are internally pulled up and may be unconnected. they may alternately be connected to v dd through a pull-up resistor. tdo should be left unconnected. upon power-up, the device comes up in a reset state which does not interfere with the operation of the device. test access port (tap) test clock (tck) the test clock is used only with the tap controller. all inputs are captured on the rising edge of tc k. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this ball unconnected if the tap is not used. the ball is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi ball is used to serially input information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information on loading the instruction register, see tap controller state diagram on page 15 . tdi is internally pulled up and can be unconnected if the tap is unus ed in an application. tdi is connected to the most signific ant bit (msb) of any register. test data-out (tdo) the tdo output ball is used to serially clock data-out from the registers. the output is active depending upon the current state of the tap state machine (see instruction codes on page 19 ). the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does no t affect the operation of the sram and may be performed while the sram is operating. at power-up, the tap is reset in ternally to ensure that tdo comes up in a high z state. tap registers registers are connected betw een the tdi and tdo balls and enable data to be scanned into and out of the sram test circuitry. only one register can be selected at a time through the instruction register. data is serially loaded into the tdi ball on the rising edge of tck. data is output on the tdo ball on the falling edge of tck. instruction register three-bit instructions can be serially loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo balls as shown in the tap controller block diagram on page 16 . upon power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as described in the previous section. when the tap controller is in th e capture-ir state, the two least significant bits are loaded with a binary ?01? pattern to enable fault isolation of the board-level serial test data path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between the tdi and tdo balls. this enables data to be shifted through the sram with minimal delay. the by pass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and bidirectional balls on the sram. the boundary scan register is loaded with the contents of the ram i/o ring when the tap controll er is in the capture-dr state and is then placed between the tdi and tdo balls when the controller is moved to the shift-dr state. the extest, sample/preload and sample z instructions can be used to capture the contents of the i/o ring. the boundary scan order on page 20 and boundary scan order on page 21 show the order in which the bits are connected. each bit corresponds to one of the bu mps on the sram package. the msb of the register is con nected to tdi and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction register . the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id regist er has a vendor code and other information described in identification register definitions on page 19 . tap instruction set overview eight different instructions ar e possible with the three-bit instruction register. all co mbinations are listed in instruction codes on page 19 . three of these instru ctions are listed as reserved and should not be used. the other five instructions are described in detail in this section.
cy7c1360c, cy7c1362c document number: 38-05540 rev. *n page 14 of 37 the tap controller used in this sram is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. the tap controller cannot be used to load address data or control signals into the sram and cannot preload the i/o buffers. the sram does not implement the 1149.1 commands extest or intest or the preload portion of sample/preload; rather, it performs a captur e of the i/o ring when these instructions are executed. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted through the instruction register through the tdi and tdo balls. to execute the instruction once it is shifted in, the tap controller needs to be moved into the update-ir state. extest extest is a mandatory 1149.1 instruction which is to be executed whenever the instruction r egister is loaded with all 0s. extest is not implemented in this sram tap controller, and therefore this device is not compliant to 1149.1. the tap controller does recognize an all-0 instruction. when an extest instruction is loaded into the instruction register, the sram respond s as if a sample/preload instruction has been loaded. there is one difference between the two instructions. unlike the sample/preload instruction, extest places the sram outputs in a high z state. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo balls and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr state. the idcode instruction is loade d into the instruction register upon power up or whenever the tap controller is given a test logic reset state. sample z the sample z instruction causes the boundary scan register to be connected between the tdi and tdo balls when the tap controller is in a shift-dr state. it also places all sram outputs into a high z state. sample/preload sample/preload is a 1149.1 mandatory instruction. when the sample/preload instruct ions are loaded into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. the user must be aware that the tap controller clock can only operate at a frequency up to 20 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possible that during the capture-dr state, an input or output will undergo a transition. the tap may then tr y to capture a signal while in transition (metastable state). this will not harm the device, but there is no guarantee as to the value that will be captured. repeatable results may not be possible. to guarantee that the boundary scan register will capture the correct value of a signal, the sram signal must be stabilized long enough to meet the tap controller?s capture setup plus hold times (t cs and t ch ). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/preload instruction. if this is an issue, it is still possible to capture all othe r signals and simply ignore the value of the ck and ck captured in the boundary scan register. after the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo pins. preload enables an initial data pattern to be placed at the latched parallel outputs of the boun dary scan register cells prior to the selection of another boundary scan test operation. the shifting of data for the sample and preload phases can occur concurrently when requir ed - that is, while data captured is shifted out, the preloaded data can be shifted in. bypass when the bypass instruction is loaded in the instruction register and the tap is placed in a shift- dr state, the bypass register is placed between the tdi and tdo balls. the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. reserved these instructions are not im plemented but are reserved for future use. do not use these instructions.
cy7c1360c, cy7c1362c document number: 38-05540 rev. *n page 15 of 37 tap controller state diagram the 0/1 next to each state represents the value of tms at the rising edge of tck. test-logic reset run-test/ idle select dr-scan select ir-scan capture-dr shift-dr capture-ir shift-ir exit1-dr pause-dr exit1-ir pause-ir exit2-dr update-dr exit2-ir update-ir 1 1 1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0
cy7c1360c, cy7c1362c document number: 38-05540 rev. *n page 16 of 37 tap controller block diagram tap timing bypass register 0 instruction register 0 1 2 identification register 0 1 2 29 30 31 . . . boundary scan register 0 1 2 . . x . . . selection circuitry tck tms tap controller tdi tdo selection circuitry t tl test clock (tck) 123456 t est mode select (tms) t th test data-out (tdo) t cyc test data-in (tdi) t tmsh t tmss t tdih t tdis t tdox t tdov dont care undefined
cy7c1360c, cy7c1362c document number: 38-05540 rev. *n page 17 of 37 3.3 v tap ac test conditions input pulse levels ...............................................v ss to 3.3 v input rise and fall times ...................................................1 ns input timing reference levels .. ....................................... 1.5 v output reference levels ................................................ 1.5 v test load termination supply voltage ............................ 1.5 v 3.3 v tap ac out put load equivalent 2.5 v tap ac test conditions input pulse levels ............ ................................... v ss to 2.5 v input rise and fall time ....................................................1 ns input timing reference levels ... .................................... 1.25 v output reference levels .............................................. 1.25 v test load termination supply vo ltage .......................... 1.25 v 2.5 v tap ac output load equivalent tap ac switchi ng characteristics over the operating range parameter [13, 14] description min max unit clock t tcyc tck clock cycle time 50 ? ns t tf tck clock frequency ? 20 mhz t th tck clock high time 20 ? ns t tl tck clock low time 20 ? ns output times t tdov tck clock low to tdo valid ? 10 ns t tdox tck clock low to tdo invalid 0 ? ns setup times t tmss tms setup to tck clock rise 5 ? ns t tdis tdi setup to tck clock rise 5 ? ns t cs capture setup to tck rise 5 ? ns hold times t tmsh tms hold after tck clock rise 5 ? ns t tdih tdi hold after clock rise 5 ? ns t ch capture hold after clock rise 5 ? ns tdo 1.5v 20pf z = 50 o 50 tdo 1.25v 20pf z = 50 o 50 notes 13. t cs and t ch refer to the setup and hold time requirements of latching data from the boundary scan register. 14. test conditions are specified using t he load in tap ac test conditions. t r /t f = 1 ns.
cy7c1360c, cy7c1362c document number: 38-05540 rev. *n page 18 of 37 tap dc electrical characteristics and operating conditions (0 c < t a < +70 c; v dd = 3.3 v 0.165 v unless otherwise noted) parameter [15] description conditions min max unit v oh1 output high voltage i oh = ?4.0 ma v ddq = 3.3 v 2.4 ? v i oh = ?1.0 ma v ddq = 2.5 v 2.0 ? v v oh2 output high voltage i oh = ?100 a v ddq = 3.3 v 2.9 ? v v ddq = 2.5 v 2.1 ? v v ol1 output low voltage i ol = 8.0 ma v ddq = 3.3 v ? 0.4 v i ol = 8.0 ma v ddq = 2.5 v ? 0.4 v v ol2 output low voltage i ol = 100 a v ddq = 3.3 v ? 0.2 v v ddq = 2.5 v ? 0.2 v v ih input high voltage v ddq = 3.3 v 2.0 v dd + 0.3 v v ddq = 2.5 v 1.7 v dd + 0.3 v v il input low voltage v ddq = 3.3 v ?0.5 0.7 v v ddq = 2.5 v ?0.3 0.7 v i x input load current gnd < v in < v ddq ?5 5 a note 15. all voltages referenced to v ss (gnd).
cy7c1360c, cy7c1362c document number: 38-05540 rev. *n page 19 of 37 identification regi ster definitions instruction field cy7c1360c (256 k 36) description revision number (31:29) 000 describes the version number device depth (28:24) [16] 01011 reserved for internal use device width (23:18) 119-ball bga 101000 defines memory type and architecture device width (23:18) 165-ball fbga 000000 defines memory type and architecture cypress device id (17:12) 100110 defines width and density cypress jedec id code (11:1) 00000110100 al lows unique identification of sram vendor id register presence indicator (0) 1 indicates the presence of an id register scan register sizes register name bit size ( 36) instruction 3 bypass 1 id 32 boundary scan order (119-ball bga package) 71 boundary scan order (165-ball fbga package) 71 instruction codes instruction code description extest 000 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all sram outputs to high z state. idcode 001 loads the id register wit h the vendor id code and places the register between tdi and tdo. this operation does not affect sram operations. sample z 010 captures i/o ring contents. places th e boundary scan register between tdi and tdo. forces all sram output drivers to a high z state. reserved 011 do not use: this instruct ion is reserved for future use. sample/preload 100 captures i/o ring contents. places the boundary sca n register between tdi and tdo. does not affect sram operation. reserved 101 do not use: this instruct ion is reserved for future use. reserved 110 do not use: this instruct ion is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operations. note 16. bit #24 is ?1? in the register definitions fo r both 2.5 v and 3.3 v versions of this device.
cy7c1360c, cy7c1362c document number: 38-05540 rev. *n page 20 of 37 boundary scan order 165-ball fbga cy7c1360c (256 k 36) bit# ball id signal name bit# ball id signal name 1b6clk 37 r6 a0 2b7gw 38 p6 a1 3a7bwe 39 r4 a 4b8oe 40 p4 a 5a8adsc 41 r3 a 6b9adsp 42 p3 a 7a9adv 43 r1 mode 8b10a 44n1dqp d 9a10a 45l2dq d 10 c11 dqp b 46 k2 dq d 11 e10 dq b 47 j2 dq d 12 f10 dq b 48 m2 dq d 13 g10 dq b 49 m1 dq d 14 d10 dq b 50 l1 dq d 15 d11 dq b 51 k1 dq d 16 e11 dq b 52 j1 dq d 17 f11 dq b 53 internal internal 18 g11 dq b 54 g2 dq c 19 h11 zz 55 f2 dq c 20 j10 dq a 56 e2 dq c 21 k10 dq a 57 d2 dq c 22 l10 dq a 58 g1 dq c 23 m10 dq a 59 f1 dq c 24 j11 dq a 60 e1 dq c 25 k11 dq a 61 d1 dq c 26 l11 dq a 62 c1 dqp c 27 m11 dq a 63 b2 a 28 n11 dqp a 64 a2 a 29 r11 a 65 a3 ce 1 30 r10 a 66 b3 ce 2 31 p10 a 67 b4 bw d 32 r9 a 68 a4 bw c 33 p9 a 69 a5 bw b 34 r8 a 70 b5 bw a 35 p8 a 71 a6 ce 3 36 p11 a
cy7c1360c, cy7c1362c document number: 38-05540 rev. *n page 21 of 37 boundary scan order 119-ball bga cy7c1360c (256 k 36) bit# ball id signal name bit# ball id signal name 1 k4 clk 37 p4 a0 2h4gw 38 n4 a1 3m4bwe 39 r6 a 4f4oe 40 t5 a 5b4adsc 41 t3 a 6a4adsp 42 r2 a 7g4adv 43 r3 mode 8c3a 44p2dqp d 9b3a 45p1dq d 10 d6 dqp b 46 l2 dq d 11 h7 dq b 47 k1 dq d 12 g6 dq b 48 n2 dq d 13 e6 dq b 49 n1 dq d 14 d7 dq b 50 m2 dq d 15 e7 dq b 51 l1 dq d 16 f6 dq b 52 k2 dq d 17 g7 dq b 53 internal internal 18 h6 dq b 54 h1 dq c 19 t7 zz 55 g2 dq c 20 k7 dq a 56 e2 dq c 21 l6 dq a 57 d1 dq c 22 n6 dq a 58 h2 dq c 23 p7 dq a 59 g1 dq c 24 n7 dq a 60 f2 dq c 25 m6 dq a 61 e1 dq c 26 l7 dq a 62 d2 dqp c 27 k6 dq a 63 c2 a 28 p6 dqp a 64 a2 a 29 t4 a 65 e4 ce 1 30 a3 a 66 b2 ce 2 31 c5 a 67 l3 bw d 32 b5 a 68 g3 bw c 33 a5 a 69 g5 bw b 34 c6 a 70 l5 bw a 35 a6 a 71 internal internal 36 b6 a
cy7c1360c, cy7c1362c document number: 38-05540 rev. *n page 22 of 37 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature .. ............... ............... ?65 c to +150 c ambient temperature with power applied ............ ............... ............... ?55 c to +125 c supply voltage on v dd relative to gnd .......?0.5 v to +4.6 v supply voltage on v ddq relative to gnd ...... ?0.5 v to +v dd dc voltage applied to outputs in tri-state ..........................................?0.5 v to v ddq + 0.5 v dc input voltage .............. .............. ..... ?0.5 v to v dd + 0.5 v current into outputs (low) ........................................ 20 ma static discharge voltage (per mil-std-883, method 3015) ......................... > 2001 v latch-up current .................................................... > 200 ma operating range range ambient temperature v dd v ddq commercial 0 c to +70 c 3.3 v ? ? 5 % / + 10% 2.5 v ? 5% to v dd industrial ?40 c to +85 c neutron soft error immunity parameter description test conditions typ max* unit lsbu logical single-bit upsets 25 c 361 394 fit/ mb lmbu logical multi-bit upsets 25 c 0 0.01 fit/ mb sel single event latch-up 85 c 0 0.1 fit/ dev * no lmbu or sel events occurred during testing ; this column represents a statistical ? 2 , 95% confidence limit calculat ion. for more details refer to application note an54908 ?accelerated neutron ser testing and calculation of terrestrial failure rates? . electrical characteristics over the operating range parameter [17, 18] description test conditions min max unit v dd power supply voltage 3.135 3.6 v v ddq i/o supply voltage for 3.3 v i/o 3.135 v dd v for 2.5 v i/o 2.375 2.625 v v oh output high voltage for 3.3 v i/o, i oh = ?4.0 ma 2.4 ? v for 2.5 v i/o, i oh = ?1.0 ma 2.0 ? v v ol output low voltage for 3.3 v i/o, i ol = 8.0 ma ? 0.4 v for 2.5 v i/o, i ol = 1.0 ma ? 0.4 v v ih input high voltage [17] for 3.3 v i/o 2.0 v dd + 0.3 v v for 2.5 v i/o 1.7 v dd + 0.3 v v v il input low voltage [17] for 3.3 v i/o ?0.3 0.8 v for 2.5 v i/o ?0.3 0.7 v i x input leakage current except zz and mode gnd ? v i ? v ddq ?5 5 ? a input current of mode input = v ss ?30 ? ? a input = v dd ?5 ? a input current of zz input = v ss ?5 ? ? a input = v dd ?30 ? a i oz output leakage current gnd ? v i ? v ddq, output disabled ?5 5 ? a notes 17. overshoot: v ih(ac) < v dd + 1.5 v (pulse width less than t cyc /2), undershoot: v il(ac) > ?2 v (pulse width less than t cyc /2). 18. t power-up : assumes a linear ramp from 0 v to v dd(min) within 200 ms. during this time v ih < v dd and v ddq < v dd .
cy7c1360c, cy7c1362c document number: 38-05540 rev. *n page 23 of 37 i dd v dd operating supply current v dd = max, i out = 0 ma, f = f max = 1/t cyc 5 ns cycle, 200 mhz ?220ma 6 ns cycle, 166 mhz ?180ma i sb1 automatic ce power-down current ? ttl inputs v dd = max, device deselected, v in ? v ih or v in ? v il , f = f max = 1/t cyc 5 ns cycle, 200 mhz ?120ma 6 ns cycle, 166 mhz ?110ma i sb2 automatic ce power-down current ? cmos inputs v dd = max, device deselected, v in ? 0.3 v or v in > v ddq ? 0.3 v, f = 0 all speeds ? 40 ma i sb3 automatic ce power-down current ? cmos inputs v dd = max, device deselected, or v in ? 0.3 v or v in > v ddq ? 0.3 v, f = f max = 1/t cyc 5 ns cycle, 200 mhz ?110ma 6 ns cycle, 166 mhz ?100ma i sb4 automatic ce power-down current ? ttl inputs v dd = max, device deselected, v in ? v ih or v in ? v il , f = 0 all speeds ? 40 ma electrical characteristics (continued) over the operating range parameter [17, 18] description test conditions min max unit capacitance parameter [19] description test conditions 100-pin tqfp max 119-ball bga max 165-ball fbga max unit c in input capacitance t a = 25 c, f = 1 mhz, v dd = 3.3 v, v ddq = 2.5 v 555pf c clk clock input capacitance 5 5 5 pf c i/o input/output capacitance 5 7 7 pf thermal resistance parameter [19] description test conditions 100-pin tqfp package 119-ball bga package 165-ball fbga package unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, according to eia/jesd51. 29.41 34.1 16.8 c/w ? jc thermal resistance (junction to case) 6.13 14.0 3 c/w note 19. tested initially and after any design or proc ess change that may affect these parameters.
cy7c1360c, cy7c1362c document number: 38-05540 rev. *n page 24 of 37 ac test loads and waveforms figure 5. ac test loads and waveforms output r = 317 ? r = 351 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.5 v 3.3 v all input pulses v ddq gnd 90% 10% 90% 10% ? 1 ns ? 1 ns (c) output r = 1667 ? r =1538 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.25 v 2.5 v all input pulses v ddq gnd 90% 10% 90% 10% ? 1 ns ? 1 ns (c) 3.3 v i/o test load 2.5 v i/o test load
cy7c1360c, cy7c1362c document number: 38-05540 rev. *n page 25 of 37 switching characteristics over the operating range parameter [20, 21] description -200 -166 unit min max min max t power v dd (typical) to the first access [22] 1?1?ms clock t cyc clock cycle time 5.0 ? 6.0 ? ns t ch clock high 2.0 ? 2.4 ? ns t cl clock low 2.0 ? 2.4 ? ns output times t co data output valid after clk rise ? 3.0 ? 3.5 ns t doh data output hold after clk rise 1.25 ? 1.25 ? ns t clz clock to low z [23, 24, 25] 1.25 ? 1.25 ? ns t chz clock to high z [23, 24, 25] 1.25 3.0 1.25 3.5 ns t oev oe low to output valid ? 3.0 ? 3.5 ns t oelz oe low to output low z [23, 24, 25] 0?0?ns t oehz oe high to output high z [23, 24, 25] ? 3.0 ? 3.5 ns set-up times t as address setup before clk rise 1.5 ? 1.5 ? ns t ads adsc , adsp setup before clk rise 1.5 ? 1.5 ? ns t advs adv setup before clk rise 1.5 ? 1.5 ? ns t wes gw , bwe , bw x setup before clk rise 1.5 ? 1.5 ? ns t ds data input setup before clk rise 1.5 ? 1.5 ? ns t ces chip enable setup before clk rise 1.5 ? 1.5 ? ns hold times t ah address hold after clk rise 0.5 ? 0.5 ? ns t adh adsp , adsc hold after clk rise 0.5 ? 0.5 ? ns t advh adv hold after clk rise 0.5 ? 0.5 ? ns t weh gw , bwe , bw x hold after clk rise 0.5 ? 0.5 ? ns t dh data input hold after clk rise 0.5 ? 0.5 ? ns t ceh chip enable hold after clk rise 0.5 ? 0.5 ? ns notes 20. timing reference level is 1.5 v when v ddq = 3.3 v and is 1.25 v when v ddq = 2.5 v. 21. test conditions shown in (a) of figure 5 on page 24 unless otherwise noted. 22. this part has a voltage regulator internally; t power is the time that the power needs to be supplied above v dd(minimum) initially before a read or write operation can be initiated. 23. t chz , t clz ,t oelz , and t oehz are specified with ac test conditions shown in part (b) of figure 5 on page 24 . transition is measured 200 mv from steady-state voltage. 24. at any given voltage and temperature, t oehz is less than t oelz and t chz is less than t clz to eliminate bus contention between srams when sharing the same data bus. these specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user condi tions. device is designed to achieve high z prior to low z under the same system conditions. 25. this parameter is sampled and not 100% tested.
cy7c1360c, cy7c1362c document number: 38-05540 rev. *n page 26 of 37 switching waveforms figure 6. read cycle timing [26] t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a1 t ceh t ces gw, bwe, bwx d ata out (q) high-z t clz t doh t co adv t oehz t co single read burst read t oev t oelz t chz adv suspends burst. burst wraps around to its initial state t advh t advs t weh t wes t adh t ads q(a2) q(a2 + 1) q(a2 + 2) q(a1) q(a2) q(a2 + 1) q(a2 + 3) a2 a3 deselect cycle burst continued with new base address dont care undefined note 26. on this diagram, when ce is low: ce 1 is low, ce 2 is high and ce 3 is low. when ce is high: ce 1 is high or ce 2 is low or ce 3 is high.
cy7c1360c, cy7c1362c document number: 38-05540 rev. *n page 27 of 37 figure 7. write cycle timing [27, 28] switching waveforms (continued) t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a1 t ceh t ces bwe, bw x d ata out (q) high-z adv burst read burst write d(a2) d(a2 + 1) d(a2 + 1) d(a1) d(a3) d(a3 + 1) d(a3 + 2) d(a2 + 3) a2 a3 data in (d) extended burst write d(a2 + 2) single write t adh t ads t adh t ads t oehz t advh t advs t weh t wes t dh t ds gw t weh t wes byte write signals are ignored for first cycle when adsp initiates burst adsc extends burst adv suspends burst dont care undefined notes 27. on this diagram, when ce is low: ce 1 is low, ce 2 is high and ce 3 is low. when ce is high: ce 1 is high or ce 2 is low or ce 3 is high. 28. full width write can be initiated by either gw low; or by gw high, bwe low and bw x low.
cy7c1360c, cy7c1362c document number: 38-05540 rev. *n page 28 of 37 figure 8. read/write cycle timing [29, 30, 31] switching waveforms (continued) t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a2 t ceh t ces bwe, bw x d ata out (q) high-z adv single write d(a3) a4 a5 a6 d(a5) d(a6) data in (d) burst read back-to-back reads high-z q(a2) q(a1) q(a4) q(a4+1) q(a4+2) t weh t wes q(a4+3) t oehz t dh t ds t oelz t clz t co back-to-back writes a1 dont care undefined a3 notes 29. on this diagram, when ce is low: ce 1 is low, ce 2 is high and ce 3 is low. when ce is high: ce 1 is high or ce 2 is low or ce 3 is high. 30. the data bus (q) remains in high z following a write cycle, unless a new read access is initiated by adsp or adsc . 31. gw is high.
cy7c1360c, cy7c1362c document number: 38-05540 rev. *n page 29 of 37 figure 9. zz mode timing [32, 33] switching waveforms (continued) t zz i supply clk zz t zzrec a ll inputs (except zz) dont care i ddzz t zzi t rzzi outputs (q) high-z deselect or read only notes 32. device must be deselected when entering zz mode. see cycle de scriptions table for all possible signal conditions to deselect the device. 33. dqs are in high z when exiting zz sleep mode.
cy7c1360c, cy7c1362c document number: 38-05540 rev. *n page 30 of 37 ordering code definitions ordering information the table below contains only the parts that are currently availa ble. if you don?t see what you are looking for, please contact your local sales representative. for more info rmation, visit the cypress website at www.cypress.com and refer to th e product summary page at http://www.cypress.com/products cypress maintains a worldwide network of offices, solution cent ers, manufacturer?s representat ives and distributors. to find th e office closest to you, visit us at http://www.cypress.com/go/datasheet/offices speed (mhz) ordering code package diagram part and package type operating range 166 cy7c1360c-166axc 51-85050 100-pin tqfp (14 20 1.4 mm) pb-free (3 chip enable) commercial cy7c1360c-166ajxc 51-85050 100-pin tqfp (14 20 1.4 mm) pb-free (2 chip enable) CY7C1362C-166AJXC cy7c1360c-166bzc 51-85180 165-ball fbga (13 15 1.4 mm) cy7c1360c-166axi 51-85050 100-pin tqfp (14 20 1.4 mm) pb-free (3 chip enable) industrial 200 cy7c1360c-200axc 51-85050 100-pin tqfp (14 20 1.4 mm) pb-free (3 chip enable) commercial cy7c1360c-200ajxc 51-85050 100-pin tqfp (14 20 1.4 mm) pb-free (2 chip enable) cy7c1360c-200bgc 51-85115 119-ball bga (14 22 2.4 mm) temperature range: x = c or i c = commercial; i = industrial pb-free package type: xx = a or aj or bz or bg a = 100-pin tqfp (3 chip enable) aj = 100-pin tqfp (2 chip enable) bz = 165-ball fbga bg = 119-ball bga speed grade: xxx = 166 mhz or 200 mhz process technology: c ? 90 nm part identifier: 13xx = 1360 or 1362 1360 = scd, 256 k 36 (9 mb) 1362 = scd, 512 k 18 (9 mb) technology code: c = cmos marketing code: 7 = sram company id: cy = cypress c 13xx c - xxx x xx cy 7 x
cy7c1360c, cy7c1362c document number: 38-05540 rev. *n page 31 of 37 package diagrams figure 10. 100-pin tqfp (14 20 1.4 mm) a100ra package outline, 51-85050 51-85050 *d
cy7c1360c, cy7c1362c document number: 38-05540 rev. *n page 32 of 37 figure 11. 119-ball pbga (14 22 2.4 mm) bg119 package outline, 51-85115 package diagrams (continued) 51-85115 *d
cy7c1360c, cy7c1362c document number: 38-05540 rev. *n page 33 of 37 figure 12. 165-ball fbga (13 15 1.4 mm) bb165d/ bw165d (0.5 ball diameter) package outline, 51-85180 package diagrams (continued) 51-85180 *f
cy7c1360c, cy7c1362c document number: 38-05540 rev. *n page 34 of 37 acronyms document conventions units of measure acronym description bga ball grid array ce chip enable cmos complementary metal oxide semiconductor eia electronic industries alliance fbga fine-pitch ball grid array i/o input/output jedec joint electron devices engineering council jtag joint test action group lmbu logical multi-bit upsets lsb least significant bit lsbu logical single-bit upsets msb most significant bit oe output enable pbga plastic ball grid array sel single event latch up sram static random access memory tap test access port tck test clock tdi test data-in tdo test data-out tms test mode select tqfp thin quad flat pack ttl transistor-transistor logic symbol unit of measure c degree celsius mhz megahertz a microampere ma milliampere mm millimeter ms millisecond mv millivolt ns nanosecond ? ohm % percent pf picofarad vvolt wwatt
cy7c1360c, cy7c1362c document number: 38-05540 rev. *n page 35 of 37 document history page document title: cy7c1360c/cy7c1362c, 9-mbit (256 k 36/512 k 18) pipelined sram document number: 38-05540 rev. ecn no. submission date orig. of change description of change ** 241690 see ecn rkf new data sheet. *a 278130 see ecn rkf updated boundary scan order (changed to match the b rev of these devices). updated boundary scan order (changed to match the b rev of these devices). updated ordering information (changed tqfp pkg to lead-free tqfp in ordering information section, added comment of lead-free bg and bz packages availability). *b 248929 see ecn vbl updated functional overview (updated zz mode electrical characteristics (changed maximum value of i ddzz parameter from 35 ma to 50 ma)). updated electrical characteristics (changed maximum value of i sb1 and i sb3 parameter as follows: i sb1 : 225 mhz -> 130 ma, 200 mhz -> 120 ma, 167 mhz -> 110 ma i sb3 : 225 mhz -> 120 ma, 200 mhz -> 110 ma, 167 mhz -> 100 ma). updated ordering information (added bg and bz pkg lead-free part numbers). *c 323636 see ecn pci updated features (changed frequency from 225 mhz to 250 mhz). updated selection guide (changed frequency from 225 mhz to 250 mhz). updated pin configurations (modified address expansion as per jedec standard). updated electrical characteristics (changed frequency from 225 mhz to 250 mhz). updated thermal resistance (changed value of ? ja and ? jc parameters for 100-pin tqfp package from 25 ? c/w and 9 ? c/w to 29.41 ? c/w and 6.13 ? c/w respectively, changed value of ? ja and ? jc parameters for 119-ball bga package from 25 ? c/w and 6 ? c/w to 34.1 ? c/w and 14.0 ? c/w respectively, changed value of ? ja and ? jc parameters for 165-ball fbga package from 27 ? c/w and 6 ? c/w to 16.8 ? c/w and 3.0 ? c/w respectively). updated switching characteristics (changed frequency from 225 mhz to 250 mhz, replaced minimum value of t cyc parameter from 4.4 ns to 4.0 ns for 250 mhz frequency). updated ordering information (removed comment of lead-free bg and bz packages availability). *d 332879 see ecn pci updated selection guide (unshaded 200 and 166 mhz frequency information). updated pin definitions (added address expansion pins). updated identification register definitions (splitted device width (23:18) into two rows, retained the same values for 165-ball fbga, changed device width (23:18) for 119-ball bga from 000000 to 101000). updated electrical characteristics (updated test conditions of v oh , v ol parameters, unshaded 200 and 166 mhz frequency information). updated switching characteristics (unshaded 200 and 166 mhz frequency information). updated ordering information (updated part numbers). *e 357258 see ecn pci changed status from preliminary to final. updated selection guide (unshaded 250 mhz frequency information). updated electrical characteristics (unshaded 250 mhz frequency information, changed maximum value of i sb2 parameter from 30 to 40 ma). updated switching characteristics (unshaded 250 mhz frequency information) updated ordering information (updated part numbers). *f 377095 see ecn pci updated electrical characteristics (updated note 18 (modified test condition from v ddq < v dd to v ddq ? v dd )).
cy7c1360c, cy7c1362c document number: 38-05540 rev. *n page 36 of 37 *g 408298 see ecn rxu changed address of cypress semiconductor corporation from ?3901 north first street? to ?198 champion court?. updated electrical characteristics (changed ?input load current except zz and mode? to ?input leakage current except zz and mode? in the description of i x parameter). updated ordering information (updated part numbers, replaced package name column with package diagram in the ordering information table). replaced three - state with tri-state in all instances across the document. *h 501793 see ecn vkn updated tap ac switching characteristics (changed minimum value of t th , t tl parameters from 25 ns to 20 ns, and maximum value of t tdov parameter from 5 ns to 10 ns). updated maximum ratings (added maximum rating for supply voltage on v ddq relative to gnd). updated ordering information (updated part numbers). *i 2756340 08/26/2009 vkn / aesa added neutron soft error immunity . updated ordering information (by including parts that are available, and modified the disclaimer for the ordering information). updated in new template. *j 3046851 10/04/2010 njy added ordering code definitions . updated package diagrams . added acronyms and units of measure . minor edits and updated in new template. *k 3052882 10/11/2010 njy updated ordering information (removed obsolete parts). *l 3367594 09/09/2011 prit updated package diagrams . updated in new template. *m 3612494 05/09/2012 prit updated features (removed 250 mhz frequency related information). updated functional description (removed the note ?for best-practices recommendations, refer to the cypress application note system design guidelines on www.cypress.com .? and its reference). updated selection guide (removed 250 mhz frequency related information). updated pin configurations (updated figure 1 (removed cy7c1362c related information, updated figure 3 (removed cy7c1362c related information), updated figure 4 (removed cy7c1362c related information)). updated functional overview (removed 250 mhz frequency related information). updated ieee 1149.1 serial boundary scan (jtag) (removed cy7c1362c related information). updated identification register definitions (removed cy7c1362c related information). updated scan register sizes (removed ?bit size ( 18)? column). updated boundary scan order (removed cy7c1362c related information). updated boundary scan order (removed cy7c1362c related information). updated electrical characteristics (removed 250 mhz frequency related information). updated switching characteristics (removed 250 mhz frequency related information). updated package diagrams (spec 51-85180 (changed revision from *c to *e)). *n 3754566 09/25/2012 prit updated package diagrams (spec 51-85115 (changed revision from *c to *d), spec 51-85180 (changed revision from *e to *f)). document history page (continued) document title: cy7c1360c/cy7c1362c, 9-mbit (256 k 36/512 k 18) pipelined sram document number: 38-05540 rev. ecn no. submission date orig. of change description of change
document number: 38-05540 rev. *n revised september 25, 2012 page 37 of 37 i486 is a trademark, and intel and pentium are registered trademarks of intel corporation. powerpc is a trademark of ibm corpor ation. all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c1360c, cy7c1362c ? cypress semiconductor corporation, 2004-2012. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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